Dr. B. Naresh Kumar Reddy

B. Naresh Kumar Reddy graduated B.Tech in Electronics and Communication Engineering from Sri Venkateswara University in 2010, M.Tech in Embedded Systems from K.L.University in 2012. He holds a Doctoral Degree in Electronics and Communication Engineering from the National Institute of Technology Goa (2018) supported by Visvesvaraya Ph.D. Scheme, Government of India. He has also spent time with Intel Technology India Pvt. Ltd., Bangalore, as the Graduate Intern Technical. He has been with the Indian Institute of Technology Delhi as a Post-Doctoral Fellow (2020-2021). Presently he is an Assistant Professor at the Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu-620015, India. He is currently involved in various teaching/research-related areas like Networks-on-Chip, Design methodologies for System-on-Chip, VLSI system design, FPGA implementation, Embedded Systems. He published more than 15 SCI Journals and 20 IEEE Conferences. He is a Senior member of IEEE and a member of ACM.

Qualification

  • B. Tech (2010), First Class in Electronics and Communication Engineering from Sri Venkateswara University, A.P., India.
  • M. Tech (2012), First Class with Distinction in Embedded Systems from K.L.University, A.P., India. 
  • Ph.D. (2018), VLSI and Embedded Systems (Visvesvaraya PhD Scheme) from National Institute of Technology, Goa, India.

Specialization

  • VLSI & Embedded Systems.

Research Credentials

Google Scholar ID: https://scholar.google.co.in/citations?user=HSqqGF4AAAAJ&hl=en

Scopus ID: https://www.scopus.com/authid/detail.uri?authorId=57802544300

ORCID ID: https://orcid.org/0000-0001-8434-3673

DBLP: https://dblp.org/pid/140/8798.html

Areas of Expertise

  • FPGA Architectures.
  • VLSI and Embedded Systems.
  • System-on-Chip / Multi Processor System-on-Chip/ Network-on-Chip.
  • Reconfigurable Architectures.
  • System design using RISC-V cores.

Experience

  • Assistant Professor, Indian Institute of Information Technology and Management-Kerala (2021- 2022).
  • Post-Doctoral Fellow, Indian Institute of Technology Delhi (2020-2021).
  • Assistant Professor, ICFAI Tech, ICFAI University (2018-2020).

Courses taught at Postgraduate and Undergraduate levels

  • Digital Circuit & Systems
  • Microprocessor and Microcontrollers
  • Embedded Systems
  • Computer Architecture & Organization
  • ARM System architecture
  • Digital VLSI Testing
  • Modelling & Synthesis with Verilog HDL
  • Functional Verification using Hardware Verification Language
  • Embedded System Design
  • FPGA based System Design

Professional society membership

  • IEEE Senior Member (Member No: 93668441).
  • ACM Member (Member No: 5553133).
  • Life Member, International Association of Engineers (Member No: 144416).

Publications

International Journals

19. (Elsevier) B. Naresh Kumar Reddy, and Subrat Kar, “Performance evaluation of modified mesh-based NoC architecture,” Computers and Electrical Engineering, Volume 104, Part A, 2022. (Impact Factor= 4.152).  https://doi.org/10.1016/j.compeleceng.2022.108404

18. (Springer) B. Naresh Kumar Reddy, B Seetharamulu, GS Krishna, BV Vani, “An FPGA and ASIC Implementation of Cubing Architecture,” Wireless Personal Communications, Vol. 125, pp. 3379-3391, 2022. (Impact Factor= 2.017). https://doi.org/10.1007/s11277-022-09715-w

17. (Springer) B. Naresh Kumar Reddy “Design and implementation of high performance and area efficient square architecture using Vedic Mathematics," Analog Integrated Circuits and Signal Processing, Vol. 102, pp. 501–506, 2020. (Impact Factor= 1.337) – Single Author https://doi.org/10.1007/s10470-019-01496-w

16. (Springer) B. Naresh Kumar Reddy, BV Vani, GB Lahari “An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata," Telecommunication Systems, Vol. 74, pp. 487–496, 2020. (Impact Factor= 2.336) https://doi.org/10.1007/s11235-020-00669-7

15. (Elsevier) B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “An Energy Efficient Fault-Aware Core Mapping in Mesh-based Network on Chip Systems,” Journal of Network and Computer Applications, Vol. 105, pp. 79-87, 2018. (Impact Factor= 7.574) https://doi.org/10.1016/j.jnca.2017.12.019

14. (Springer) B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Hardware Implementation of Fault Tolerance NoC Core Mapping,” Telecommunication Systems (TELS), Vol 68, pp. 621- 630, 2018. (Impact Factor= 2.336)  https://doi.org/10.1007/s11235-017-0412-2

13. (Springer) B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Energy- Aware and Reliability- Aware Mapping for NoC-Based Architectures,” Wireless Personal Communications, Vol. 100, pp. 213- 225, 2018. (Impact Factor= 2.017) https://doi.org/10.1007/s11277-017-5061-y

12. (Elsevier) B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “System Level Fault-Tolerance Core Mapping and FPGA-based Verification of NoC," Microelectronics Journal, Vol. 70, pp. 16- 26, 2018. (Impact Factor= 1.992) https://doi.org/10.1016/j.mejo.2017.09.010

11. (Elsevier) B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “High- Performance and Energy-Efficient Fault-Tolerance Core Mapping in NoC,” Sustainable Computing, Informatics and Systems, Vol. 16, pp. 1- 10, 2018. (Impact Factor= 4.923) https://doi.org/10.1016/j.suscom.2017.08.004

10. (Springer) B. Naresh Kumar Reddy, C Ramalingaswamy, R Nagulapalli, D Ramesh “A novel 8T SRAM with improved cell density,” Analog Integrated Circuits and Signal Processing, Vol. 98, Issue 2, pp. 357-366, 2019. (Impact Factor= 1.321) https://doi.org/10.1007/s10470-018-1309-z

9. (Springer) B. Naresh Kumar Reddy, Dharavath Kishan, and B. Veena Vani, “Performance constrained multi-application network on chip core mapping,” International Journal of Speech Technology, Vol 22, pp.927-936, 2019. https://doi.org/10.1007/s10772-019-09636-3

8. (Springer) A. Sai Kumar and B. Naresh Kumar Reddy, “An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip,” Wireless Personal Communications, Vol 128, pp.2937-2952, 2023. (Impact Factor= 2.017) https://doi.org/10.1007/s11277-022-10080-x 

7. (Springer) K. Raghava Rao, B. Naresh Kumar Reddy, and A. Sai Kumar “Using advanced distributed energy efficient clustering increasing the network lifetime in wireless sensor networks,”  Soft Computing, 2023. (Impact Factor= 3.732) https://doi.org/10.1007/s00500-023-07940-4

6. (Inderscience) A. Sai Kumar, TVK H Rao and B. Naresh Kumar Reddy, “Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures,” International Journal of Ad Hoc and Ubiquitous Computing, Vol 41, pp. 108-117, 2022. (Impact Factor= 0.773) https://doi.org/10.1504/IJAHUC.2022.125427

5. (IEEE) K. Raghava Rao, Md Zia Ur Rahman, Krishna Prasad Satamraju and  B Naresh Kumar Reddy, “Genetic Algorithm for Cross-Layer based Energy Hole Minimization in Wireless Sensor Networks,” IEEE Sensors Letters, 2022. (Impact Factor= 3.04) https://doi.org/10.1109/LSENS.2022.3219857

4. (Springer) Pittala, C.S., Vijay, V. and B. Naresh Kumar Reddy, “1-Bit FinFET Carry Cells for Low Voltage High-Speed Digital Signal Processing Applications,” Silicon (2022). (Impact Factor= 2.941) https://doi.org/10.1007/s12633-022-02016-8

3. (Springer) Javvaji, V., Musala, S. and B. Naresh Kumar Reddy, “Continuous-time complex band-pass Gm-C sigma delta ADC with programmable bandwidths,” Analog Integrated Circuits and Signal Processing, Vol. 108, pp. 267–276, 2021. (Impact Factor= 1.337) https://doi.org/10.1007/s10470-021-01866-3

2. (Springer) Ahmed, S., Ramesh, N.V.K. and B. Naresh Kumar Reddy, “A Highly Secured QoS Aware Routing Algorithm for Software Defined Vehicle Ad-Hoc Networks Using Optimal Trust Management Scheme,” Wireless Personal Communications, Vol. 113, pp. 1807–1821, 2020. (Impact Factor= 2.017) https://doi.org/10.1007/s11277-020-07293-3

1. (Springer) Yehoshuva, C., B. Naresh Kumar Reddy., Ambati, V.R., “A novel CMOS Gmm-C complex filter design for multi-mode multi band wireless receiver applications,” Analog Integrated Circuits and Signal Processing, Vol. 91, pp. 43–51, 2017. (Impact Factor= 1.321) https://doi.org/10.1007/s10470-016-0823-0

International Conferences

13. B Naresh Kumar Reddy, Alex James and Sai Kumar, “Fault-tolerant Core Mapping for NoC Based Architectures with Improved Performance and Energy Efficiency,” 29th International Conference on Electronics, Circuits, and Systems (ICECS-2022), Glasgow, UK, Oct 24-26, 2022. https://doi.org/10.1109/ICECS202256217.2022.9970825

12. B Naresh Kumar Reddy and A. Sai Kumar, “An Efficient Low-Power VIP-based VC Router Architecture for Mesh-based NoC,” IEEE 19th Indian Council International Conference (INDICON), Nov 24-26, 2022. https://doi.org/10.1109/INDICON56171.2022.10040017

11. B Naresh Kumar Reddy and Subrat Kar “An Efficient Application Core Mapping Algorithm for Wireless Network-on-Chip,” 26th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2021), Dec 1– 4, in Perth, Australia, 2021. https://doi.org/10.1109/PRDC53464.2021.00028

10. B Naresh Kumar Reddy and Subrat Kar “Energy Efficient and High Performance Modified Mesh Based 2-D NoC Architecture,” 22nd IEEE International Conference on High Performance Switching and Routing (HPSR), June 7 – 9, in Paris, France, 2021. https://doi.org/10.1109/HPSR52026.2021.9481796

9. Sudheer H, G Sai Vishal Reddy and B Naresh Kumar Reddy, “Design and Analysis of High Reliable Fault Tolerance Subsystem for Micro Computer Systems,” 11th IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE 2021), Penang, Malaysia, pp. 127-130, 2021. https://doi.org/10.1109/ISCAIE51753.2021.9431830

8. Sai Kumar, T.V.K.Hanumatha Rao and B. Naresh Kumar Reddy, “Exact Formulas for Fault Aware Core Mapping on NoC Reliability,” 17th International IEEE India Conference INDICON, 2020. https://doi.org/10.1109/INDICON49873.2020.9342427

7. B Naresh Kumar Reddy, G Sai Vishal Reddy, B Veena Vani, “Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates,” IEEE Bombay Section Signature Conference (IBSSC), pp. 247-250, 2020. https://doi.org/10.1109/IBSSC51096.2020.9332213

6. B. Naresh Kumar Reddy, Sarangam K, T. Veeraiah and Ramalingaswamy Cheruku "SRAM cell with better read and write stability with Minimum area," IEEE TENCON 2019. https://doi.org/10.1109/TENCON.2019.8929593

5. B. Naresh Kumar Reddy and Sireesha, “An Efficient Core Mapping Algorithm on Network on Chip,” 22nd International Symposium on VLSI Design and Test (VDAT), 2018. https://doi.org/10.1007/978-981-13-5950-7_52

4. B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare core,” 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), Pennsylvania, U.S.A., pp. 146-151, 2016. https://doi.org/10.1109/ISVLSI.2016.80

3. Vijaya Sree Boddu, B. Naresh Kumar Reddy and M. Kranthi Kumar, “Low-Power and Area Efficient N-bit Parallel Processors on a Chip,” 13th International IEEE India Conference INDICON 2016, pp. 1-4, 2016. https://doi.org/10.1109/INDICON.2016.7839082

2. B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “Communication Energy Constrained Spare Core on NoC,” 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Dallas, U.S.A., pp. 1-4, 2015. https://doi.org/10.1109/ICCCNT.2015.7395168

1.B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “A Fine Grained Position for Modular Core on NoC,” IEEE International Conference on Computer, Communication and Control, Sep 2015. https://doi.org/10.1109/IC4.2015.7375574

Contact Address

Dr. B. Naresh Kumar Reddy

Assistant Professor (Grade-II)

Room No: 304 

Department of Electronics and Communication Engineering,

National Institute of Technology,

Tiruchirappalli - 620 015, Tamil Nadu.

Mobile: +91-9966539090

E-mail: bnkreddy@nitt.edu, naresh.nitg@gmail.com