EC806

Analysis and Design of Digital Systems using VHDL (3 – 0 -0) 3

COURSE OBJECTIVES

  • To prepare the student to understand the VHDL language feature to realize the complex digital systems.
  • To design and simulate sequential and concurrent techniques in VHDL.
  • To explain modeling of digital systems using VHDL and design methodology
  • To explain predefined attributes and configurations of VHDL.
  • To Understand  behavioral, non-synthesizable VHDL and its role in modern design

 

COURSE CONTENT

An overview of design procedures for system design using CAD tools. Design verification tools. Examples using commercial PC based VLSI CAD tools. Design methodology based on VHDL. Basic concepts and structural descriptions in VHDL.

Characterizing hardware languages, objects and classes, signal assignments, concurrent and sequential assignments. Structural specification of hardware.

Design  organization,  parameterization  and  high  level  utilities,  definition  and  usage  of  subprograms, packaging parts and utilities, design parameterization, design configuration, design libraries. Utilities for high-level descriptions.

Data flow and behavioral description in VHDL- multiplexing and data selection, state machine description, open collector gates, three state bussing, general dataflow circuit, updating basic utilities. Behavioral description of hardware.

CPU modeling for discrete design- Parwan CPU, behavioral description, bussing structure, data flow, test bench, a more realistic Parwan. Interface design and modeling. VHDL as a modeling language.

Text Books

1.   Z.Navabi, “VHDL Analysis and Modeling of Digital Systems”, (2/e), McGraw Hill, 1998.

2.   Perry, “VHDL (3/e)”, McGraw Hill.2002

 

Reference Books

1.   A. Dewey, “Analysis and Design of Digital Systems with VHDL”, CL-Engineering, 1996.

2.   Z.Navabi ,”VHDL: modular design and synthesis of cores and systems”, McGraw, 2007.

3.   C. H. Roth, Jr., L.K.John, “Digital Systems Design Using VHDL - Thomson Learning EMEA”, Limited, 2008

 

COURSE OUTCOMES

Students are able to

CO1: model, simulate, verify, and synthesize with hardware description languages.

CO2:  understand  and  use  major  syntactic  elements  of  VHDL  -  entities,  architectures,  processes, functions, common concurrent statements, and common sequential statements

CO3: design digital logic circuits in different types of modeling

CO4: demonstrate timing and resource usage associated with modeling approach. CO5: use computer-aided design tools for design of complex digital logic circuits