- Departments / Centres
Different types of graphs. Combinational optimization- Graph optimization problems and algorithms.
Boolean functions, statisfiability and cover. Abstract models, state diagrams. Data flow and sequencing graphs , compilation and behavioural optimization.
Architectural synthesis - Circuit specifications for architectural synthesis . Temporal domain, spatial domain , hierarchical models. Synchronization problems Area and performance estimation. Strategies for architectural optimization, Data path synthesis of pipelined circuits.
Scheduling algorithms-Scheduling with and without constraints. Scheduling algorithms for extended sequencing models. Scheduling pipelined circuits.
Resource sharing and binding. Sharing and binding for resource dominated circuits and general circuits. Concurrent binding and scheduling. Resource sharing and binding for non-scheduled sequencing graphs.
Sequential logic optimization-sequential circuit optimization using state based models and network models. Implicit finite state machine. Traversal methods. Testability considerations for synchronous circuits.
1. G.De Micheli, “Synthesis and optimization of Digital circuits”, McGraw Hill,1994 .
2. C. Roth, “Fundamentals of Digital Logic Design”, Jaico Publishers, V ed., 2009.
3. Balabanian, “Digital Logic Design Principles”, Wiley publication, 2000.
1. J. F. Wakerly,”Digital Design principles and practices”, 3rd edition, PHI publication, 1999.
2. S.Brown, “Fundamentals of digital logic”, Tata McGraw Hill publication, 2007.
3. N. N. Biswas, “Logic Design Theory”, Prentice Hall of India, 2001.
4. John M Yarbrough, “Digital Logic applications and Design”, Thomson Learning, 2001.
Students are able to
CO1: understand advanced state of art techniques of digital design.
CO2: synthesis the circuits and evaluate its performance in terms of area, power and speed.
CO3: understand the use of scheduling algorithm.
CO4: gain in-depth knowledge of sequential digital circuits designed using resource sharing.
CO5: understand synchronization across clock domains, timing analysis, and Testability considerations