VLSI Digital Signal Processing Systems 3 - 0 - 0 - 3


  • To give an in-depth coverage of advanced VLSI Digital Signal Processing Systems.
  • To provide knowledge about the effect of finite word length.
  • To learn regarding the efficient implementation of arithmetic units.



Algorithms for fast convolution, Algorithmic strength reduction in filters and transforms: Parallel FIR Filters, DCT and inverse DCT, Parallel Architectures for Rank-Order Filters.

Scaling and Round off Noise - State variable description of digital filters, Scaling and Round off Noise computation, Round off Noise in Pipelined IIR Filters, Round off Noise Computation using  state variable description, Slow-down, Retiming and Pipelining.

Bit level arithmetic Architectures- parallel multipliers, interleaved floor-plan and bit-plane-based digital filters, Bit serial multipliers, Bit serial filter design and implementation, Canonic signed digit arithmetic, Distributed arithmetic.

Redundant  arithmetic  -Redundant  number  representations,  carry  free  radix-2  addition  and  subtraction, Hybrid radix-4 addition, Radix-2 hybrid redundant multiplication architectures, data format conversion, Redundant to Nonredundant converter.

Numerical   Strength   Reduction   -   Subexpression   Elimination,   Multiple   Constant   Multiplication, Subexpression Sharing in Digital Filters, Additive and Multiplicative Number Splitting.


Text Book

1.   K.K.Parhi, “VLSI Digital Signal Processing Systems”, John-Wiley, 2007


Reference Books

1.   U. Meyer -Baese, Digital Signal Processing with FPGAs, Springer, 2004

2.   Wayne Burleson, Konstantinos Konstantinides, Teresa H. Meng, VLSI Signal Processing,1996.

3.   Richard J. Higgins, Digital signal processing in VLSI, 1990.

4.   Sun Yuan Kung, Harper J. Whitehouse, VLSI and modern signal processing, 1985

5.   Magdy A. Bayoumi, VLSI Design Methodologies for Digital Signal Processing, 2012

6.   Earl E. Swartzlander, VLSI signal processing systems, 1986.



Students are able to

CO1: learn various transforms and its corresponding architectures

CO2: acquire the knowledge of effect of round off  noise computation

CO3: design Bit level arithmetic Architectures and optimize the implementation of FIR filters and constant multipliers

CO4: design basic arithmetic units and realize their architecture for higher radices

       CO5: learn different numerical strength reduction techniques