Dr. R. K. Kavitha


Email Address

Formula: 0


  • Ph.D. (2021) - "Asynchronous System Design" from  NIT Trichy
  • M.S. (2005) in Electronics and Computer Science Engineering from POSTECH, South Korea
  • B.E. (2001) in Electronics and Communication Engineering from Bharathidasan University

Positions Held

  • 2007 onwards - Assistant Professor, NIT Trichy

Area Of Interests

  • Asynchronous System Design
  • Low power VLSI system design
  • Quantum Photonics integrated design
  • In-Memory Computing, Compute SRAM design

Area Of Research

  • Asynchronous System Design
  • Memory Design
  • In-Memory-Computation

Projects Guidance

Ph.D. - Ms. Biby Joseph - Ongoing

PG - 53 Projects

UG - 20 Projects



  1. Absel, L. Manuel and R. K. Kavitha, "Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 9, pp. 1693-1704, Sept. 2013. doi: 10.1109/TVLSI.2012.2213280
  2. K. Midhun, J. Joy and R. K. Kavitha, "High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2235-2239, Oct. 2014. doi: 10.1109/TVLSI.2013.2282834
  3. Kavitha, R. K.; Toms, Vineeth Johns; Vinayakan, Vipin; Venkataramani, B. Low Power Data Driven Conditional Precharge Dynamic Flip Flop, Journal of Low Power Electronics, American Scientific Publishers Volume 13, Number 4, December 2017, pp. 569-575(7)
  4. R.K. Kavitha, A. Khajamastan, Y. Rama Akhilesh, B. Venkataramani, "High-performance asynchronous pipeline using embedded delay element", Microprocessors and Microsystems, Volume 73, 2020, https://doi.org/10.1016/j.micpro.2019.102955.
  5. R.K.Kavitha, A KhajaMastan, and B.Venkataramani, "Low-Power High-Speed Asynchronously Pipelined 24-Bit Phase accumulator For DDFS" Microprocessors and Microsystems (Under review)



  1. Srinivas Jagarapu and R.K.Kavitha. A 2.4 GHz Low Noise Amplifier in 0.18um CMOS Technology. IJCA Proceedings on International Conference on VLSI, Communications and Instrumentation (ICVCI) (10):10–15, 2011.
  2. Manuel, L., Midhun, C. K., & Kavitha, R. K. “High speed dynamic asynchronous pipeline: Self-Controlled approach”.  India Conference (INDICON), 2012 Annual IEEE (pp. 592-596). 
  3. T Saravanan and R.K. Kavitha,”Dual Current Reuse Ultra Wide Band Low Noise Amplifier”International Conference on Communication and Signal Processing (ICCSP ’13), Apr-2013, India.
  4. Mohammed Abbas, C.; Shukla, A.; Kavitha, R.K., "Sub-1V ultra low-power voltage reference," in VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on , vol., no., pp.1-4, 8-10 Jan. 2015
  5. S. K. Raman, J. K. Jayaram, S. Murugan, A. Saha and R. K. Kavitha, "Design of a robust method to acquire EOG signals using Bio-medical signal processing," 2016 Online International Conference on Green Engineering and Technologies (IC-GET), 2016, pp. 1-4, doi: 10.1109/GET.2016.7916631.
  6. R. K. Kavitha, P. R. Rahul, P. P. Aswin and B. Venkataramani, "High Speed Synchronization Using Modified Pausible Clocking Method," 2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 2019, pp. 1-5,
  7. Naveen, A., Priyanka, C.V., Kavitha, R.K. (2022). Design and Analysis of Multiplexer Based D-Flip Flop Using QCA Implementation. In: Dhawan, A., Tripathi, V.S., Arya, K.V., Naik, K. (eds) Recent Trends in Electronics and Communication. Lecture Notes in Electrical Engineering, vol 777. Springer, Singapore. https://doi.org/10.1007/978-981-16-2761-3_17
  8. S. Yadav, Y. Bansal, B. Joseph and R. K. Kavitha, "Low-Power Dual-Vt 7T SRAM Bit-Cell With Reduced Area and Leakage," 2022 IEEE Delhi Section Conference (DELCON), 2022, pp. 1-5, doi: 10.1109/DELCON54057.2022.9753131.

Academic/Administrative Responsibilities

Institute Level

  • Ph.D. Admission Committee Member - 2022 Onwards
  • Advisory & Sub Committees for Online and Continuing Education Programs Member -2021 onwards
  • NSS Program Officer -2008-2019
  • Convocation Committee Member


Department Level

  • NBA Core committee member
  • PG- Project project Evaluation Committee Member
  • PG - Class Co-ordinator/ project phase Co-ordinator
  • Electronic Devices and Integrated Circuit Engineering (E-DICE) Lab - In-Charge
  • VLSI Lab- Additional In-charge

 Abroad Visit

  • Pohang University of Science and Technology (POSTECH), Pohang, Sough Korea from Jan 2003 to Feb 2005 for M.S.

Professional Society Membership

  • Member, IEEE (VLSI)
  • Life Member in ISTE


  • magna cum laude in M.S
  • Bharathidasan University 13th rank in B.E.

Contact Address

Dr. R.K. Kavitha
Assistant Professor
Electronics and Communication Engineering
NIT Tiruchirapalli-620015