Publications

Papers published in journals

  • S. Ramasamy , B. Venkataramani,  “A Low Power Reconfigurable Analog Baseband Block for Software Defined Radio” Journal of signal processing system, Springer, USA., (2011) 6, pp :131–144
  • Manikandan, J. and B.Venkataramani, Design of a Real Time Automatic Speech Recognition System using modified one against all SVM Classifier. Elsevier Microprocessors and Microsystems, Aug 2011, 35(6), pp.568-578.
  • J. Manikandan, B. Venkataramani, “Study and Evaluation of a Multi-class SVM Classifier using Diminishing Learning Technique”,  Elsevier journal on Neurocomputing, Volume 73 Issue 10-12, June, 2010
  • B.Malarkodi, B.Prasana and B.Venkataramani, “A Battery Power Scheduling Policy with Hardware Support In Mobile Devices ” International journal on applications of graph theory in wireless ad hoc networks and sensor networks , September 2010, Volume 2, Number 3.
  • B. Malarkodi, S. K. Riyaz Hussain, and B. Venkataramani, “Performance Evaluation of AOMDV-PAMAC Protocols for Ad Hoc Networks” WSAET, Vol 62,  pp 539-542, Feb 2010
  • B.Malarkodi, B.Venkataramani,” Protocols for increasing the lifetime of nodes of ad hoc wireless networks “International Journal on communication technology” IJCT.Volume 1, pp.7-16, February 2010.
  • G. Seetharaman, B.Venkataramani, “Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits”, ACM Transactions on Reconfigurable Technology and Systems, Vol. 2, No. 2, 11:1-11:19, June 2009
  • S. Ramasamy, B. Venkataramani* and P. Meenatchisundaram, “A low power CMOS voltage reference circuit with sub threshold MOSFETs”, Int. J. Information and Communication Technology, Vol. 2, Nos. 1/2, 2009, pp 94-107.
  • V Amudha and B. Venkataramani, “System on programmable chip implementation of neural network-based isolated digit recognition system”, International Journal of Electronics, Vol. 96, No. 2.,Feb 2009, pp. 153-163.
  • V. Amudha, B.Venkataramani, R. Vinoth kumar and S. Ravishankar, “Software/Hardware Co-Design of HMM Based Isolated Digit Recognition System”, Journal Of Computers, Vol. 4, No. 2, February 2009, pp 154-159.
  • G. Seetharaman, B.Venkataramani and G.Lakshminarayanan, "Design and FPGA implementation of self-tuned wave pipeline filters with Distributed Arithmetic Algorithm", Circuits Syst Signal Process, Birkhäuser Boston 2008 pp 261–276.
  • G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, “Automation techniques for implementation of hybrid wave-pipelined 2D DWT”, Journal on Real time image processing, Springer Verlag ,USA, Vol 3, No. 3, 2008, pp 217-229.
  • G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, Hybrid wave-pipelined 2D DWT using lifting Scheme," VLSI design, Hindawii journal,2008 pp 1-8
  • G.Seetharaman, B.Venkataramani and G.Lakshminarayanan, "Design and FPGA implementation of self tuned wave pipeline filters", Transaction of IETE journal of research, vol. 52, No. 4, pp 281-286, July-August 2006.
  • B.Malarkodi, B.Venkataramani and X.T. Pradeep, "Performance evaluation of AODV protocol with black list table for prevention of Denial of service attacks in wireless Ad hoc networks" WSEAS Transactions on Communications, Issue 1, volume 5, pp 107-114, Januray 2006.
  • V. Amudha, B. Venkataramani and G.Seetharaman, "Design and system on chip implementation of image encoders", WSEAS transactions on Circuits & Systems , Issue 10, Vol. 4, pp 1292-1299, October 2005.
  • G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, "Design and FPGA implementation of wave pipelined lifting scheme for two level 2D-DWT", WSEAS transactions on Circuits & Systems, Issue 10, Vol. 4, pp 1284-1291, October 2005.
  • G. Lakshminarayanan, B. Venkataramani, "Optimization techniques for FPGA based wave-pipelined DSP blocks", Proc. of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, no. 7, pp 783-793, July 2005.
  • B. Venkataramani, Sanjay K. Bose, K.R. Srivathsan, "Queueing analysis of a non-preemptive MMPP/D/1 priority system", Computer Communications (20), 1997, pp 999-1018.

International Conference papers

 

  • Bhaskar, M.; Parthiban, D.; Venkataramani, B.; "Design and implementation of surfing scheme to wave pipelined differential serial interconnect" , Proceedings of  IEEE conference RAICS 2011, pp 232 - 235
  • Bhaskar, M.; Sridevi, D.; Venkataramani, B.; "A low power, low latency tunable Quasi-resonant interconnect using active inductor',  Proceedings of  IEEE conference RAICS 2011, pp 295 - 298
  • Karutharaja, V; Bhaskar, M.; Venkataramani, B.; "Synchronization of on-chip serial interconnect transceivers using Delay Locked Loop (DLL)", Proceedings of IEEE conference ICSCCN, 2011, pp 213 - 216
  • S.Kumaravel, B.Venkataramani and Aryam Gupta, VLSI Implementation of Gm-C filter using Modified Nauta OTA with double CMOS pair, Proceedings of  IEEE conference RAICS 2011, pp 216 - 220
  • J. Manikandan, B. Venkataramani, K. Girish, H. Karthic, V. Siddharth, “Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP” 24th International Conference on VLSI Design, pp.250-255, January, 2011
  • B.Malarkodi, SK.Riyas Hussain, B.Venkataramani,” Performance evaluation of AOMDV-PAMAC protocols for adhoc networks" International Conference on Computer, Electrical, and Systems Science and Engineering ICCESSE 2010, Malaysia,Vol 62, pp. 1201-1204, Feb 2010
  • B.Malarkodi, S.Bavadharini, B.Venkataramani,” Power Aware MAC protocol for wireless Adhoc networks “ IEEE sponsored International conference on recent advancements in electrical  sciences,ICRAES 2010, pp. 220-224  Jan 2010.
  • Malarkodi, B.; Gopal, P.; Venkataramani, B., “Performance Evaluation of Adhoc Networks with Different Multicast Routing Protocols and Mobility Models”, Proc. Of International Conference on Advances in Recent Technologies in Communication and Computing, 2009. Page(s): 81 - 84
  • B.Malarkodi, B.Prasanna, B.Venkataramni, " A scheduling policy for battery management in mobile devices", NETCOM IEEE International Conference 09, Chennai, pp 83-88, December 27,  2009.
  • S Ramasamy B Venkataramani, , Venkata Subba reddy,“A low power tuning scheme for low frequency Continuous time filters” IEEE Region 10 conference TENCON2009, 23-26 Nov 2009
  • Sanjay Talekar, S Ramasamy, G Lakshminarayanan, B Venkataramani “A low power 700MSPS 4bit time interleaved SAR ADC in 0.18um CMOS ”, IEEE Region 10 conference TENCON2009, 23-26 Nov 2009
  • Manikandan J, B Venkataramani, P Preethi, G Sananda, K V Sadhana, “Implementation of a Phoneme Recognition System using Zero-Crossing and Magnitude Sum Function” IEEE Region 10 conference TENCON2009, 23-26 Nov 2009
  • Manikandan, J.; Venkataramani, B.; “Design of a modified one-against-all SVM classifier”, IEEE International Conference on Systems, Man and Cybernetics, 2009. SMC 2009. 11-14 Oct. 2009 Page(s):1869 - 1874
  • Malarkodi, B.; Rakesh, P.; Venkataramani, B.; “Performance Evaluation of On-Demand Multipath Distance Vector Routing Protocol under Different Traffic Models”, International Conference on Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. 27-28 Oct. 2009 Page(s):77 – 80
  • Malarkodi, B.; Gopal, P.; Venkataramani, B.; “Performance Evaluation of Adhoc Networks with Different Multicast Routing Protocols and Mobility Models”, International Conference on Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. 27-28 Oct. 2009 Page(s):81 - 84
  • Talekar, S.G.; Ramasamy, S.; Lakshminarayanan, G.; Venkataramani, B.; 500MS/s 4-b time interleaved SAR ADC using novel DAC architecture Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on 15-16 July 2009 Page(s):292 - 297
  • Kirankumar,M.Bhaskar,R.Thilagavathy and B.Venkataramani, “A Novel Low Power Multilevel Current Mode Interconnect System Ineffective to Supply voltage variations”, International Conference on Optoelectronics and Communication Technology ICOICT2009, Trivandum, February 2009.
  • Venkateswaralu, M.Bhaskar and B.Venkataramani ‘Quasi-resonant interconnects: Programmable data rate implementation using active inductor’, International Conference on Optoelectronics and Communication Technology ICOICT2009,Trivandum, 26-27 February 2009
  • Ramasamy, S.; Venkataramani, B.; Niranjini, R.; Suganya, K.;100KHz-20MHz Programmable Subthreshold G_m-C Low-Pass Filter in 0.18µ-m CMOS, 22nd International Conference on VLSI Design, 2009, 5-9 Jan. 2009 pp:105 – 110
  • Ramasamy, S.; Venkataramani, B.; Meenatchisundaram, P.;A low power CMOS voltage reference circuit with subthreshold MOSFETs, International Conference on Electronic Design, 2008. ICED 2008, 1-3 Dec. 2008 Page(s):1 - 6
  • Ramasamy, S.; Venkataramani, B.; Meenatchisundaram, P.;A low power programmable band gap reference circuit with subthreshold MOSFETs, IEEE Region 10 Conference TENCON 2008, 19-21 Nov. 2008 Page(s):1 - 6
  • Ramasamy, S.; Venkataramani, B.; Stalin, S.M.; Venkatachalam, K.Tunable band pass Gm-C filter with switched transconductance cells; IEEE Region 10 Conference TENCON 2008, 19-21 Nov. 2008 Page(s):1 - 5
  • Manikandan, J.; Venkataramani, B.;Diminishing learning based SVM classifier with non-linear kernels, International Conference on Electronic Design, 2008. ICED 2008. 1-3 Dec. 2008 Page(s):1 - 6
  • Amudha, V.; Venkataramani, B.; Manikandan, J., FPGA implementation of isolated digit recognition system using modified back propagation algorithm; International Conference on Electronic Design, 2008. ICED 2008. 1-3 Dec. 2008 Page(s):1 - 6
  • Manikandan, J.; Venkataramani, B.; Avanthi, V.;FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System, 22nd International Conference on VLSI Design, 2009, 5-9 Jan. 2009 Page(s):347 – 352
  • Manikandan, J.; Venkataramani, B.; Amudha, V.; Arafat, A.Majed; Sahu, Hruday A novel technique for Support Vector Machine based multi-class classifier; IEEE Region 10 Conference TENCON 2008 19-21 Nov. 2008 Page(s):1 – 6
  • Anusha, G.; Venkateshwarlu, P.; Murugeshwari, P.; Bhaskar, M.; Venkataramani, B.;An input multiplexed current mode transmitter for on-chip global interconnects, IEEE Region 10 Conference TENCON 2008, 19-21 Nov. 2008 Page(s):1 – 5
  • Murugeswari, P.; Anusha, G.; Venkateshwarlu, P.; Bhaskar, M.; Venkataramani, B.;A wide band voltage mode sense amplifier receiver for high speed interconnects IEEE Region 10 Conference TENCON 2008, 19-21 Nov. 2008 Page(s):1 – 5
  • Vireen, V.; Seetharaman, G.; Venkataramani, B.;Synthesis techniques for implementation of wave-pipelined circuits in ASICs, International Conference on Electronic Design, 2008.1-3 Dec. 2008 Page(s):1 – 6
  • Venugopalachary, N.; Vireen, V.; Seetharaman, G.; Venkataramani, BASIC implementation of self tuned wave-pipelined circuits.; International Conference on Electronic Design, 2008. 1-3 Dec. 2008 Page(s):1 – 6
  • Vireen, V.; Venugopalachary, N.; Seetharaman, G.; Venkataramani, B.;Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs, 22nd International Conference on VLSI Design, 2009, 5-9 Jan. 2009 Page(s):473 – 478
  • J. Manikandan, B. Venkataramani and M. Jayachandran, “Evaluation of Edge Detection Techniques towards Implementation of Automatic Target Recognition”, Proc. of the International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007) Vol: 02, pp 441-445
  • S. Ramasamy, B. Venkataramani, K. Anbugeetha, "VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair", Proc. Of IEEE international conference on VLSI Design, 2008, Pages 317-322
  • G. Seetharaman, B. Venkataramani, "SOC implementation of wave-pipelined circuits", Proc. Of IEEE international conference on Field Programmable Techology 2007, Kitakyushu, Japan, pp 9-16
  • V.Amudha, B.Venkataramani,R.Vinoth kumar and S. Ravishankar “SOC implementation of HMM based speaker independent isolated digit recognition” Proc. Of IEEE international conference on VLSI Design, 2008
  • V. Amudha , B. Venkataramani and G. Seetharaman, “Optimisation techniques for the system on chip implementation of JPEG encoder”, Proc. of the 5th WSEAS Int. Conf. on Signal Processing, Computational Geometry & Artificial Vision, Malta, September 15-17, 2005, pp 94-101
  • G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, “Design and FPGA implementation of lifting scheme for 2D-DWT using wavepipelining”, Proc. of the 5th WSEAS Int. Conf. on Signal Processing, Computational Geometry & Artificial Vision, Malta, September 15-17, 2005, pp 53-60
  • B. Malarkodi, B. Venkataramani and X.T. Pradeep, “Modified AODV protocol for prevention of Denial of service attacks in wireless Ad hoc networks”, Proc. of the 5th WSEAS Int. Conf. on Applied informatics and communications, Malta, September 15-17, 2005 pp 77-84
  • G. Seetharaman, B.Venkataramani, V. Amudha, Anurag Saundattikar, “System on chip implementation of 2D DWT using lifting scheme”, Proc. of the International Asia and South Pacific Conference on Embedded SOCs (ASPICES 2005), July 5-8, 2005, Bangalore
  • G.Lakshminarayanan, B.Venkataramani, J.Senthil Kumar, A.K. Md, Yousuf, G.Sriram, M.S.Jambunathan,“Design and FPGA implementation of image block encoders with 2D-DWT”, Proc. TENCON 2003, Bangalore, Oct 15-17, 2003, Vol III, pp 1015-1019
  • G.Lakshminarayanan, B.Venkataramani, M.Sasitharan , K.P.Senthil Kumar, "Design and implementation of FPGA based wavepipelined multiplier accumulators", Proc. Of the International Conf. on Circuits, Control, Communication and Devices ICCCD 2000, IIT, Kharagpur, Dec 2000, pp 265-268
  • G.Lakshminarayanan,B.Venkataramani,K.P.SenthilKumar, M.Sasitharan, V.A.K. Kottapalli “ Design and Implementation of a FPGA based wavepipelined fast convolver” Proc. of the international conf. TENCON 2000, Kuala lumpur, Malaysia, Sep 24-27, 2000, Vol III, pp 212-217
  • G.Lakshminarayanan, Boby George, B. Venkataramani ,A.Ramakalyan," Neural Network Controlled Shift Register Traffic Shaper for ATM Networks", Proceedings of IEEE TENCON '98, December 1998, pp: 33-36
  • B. Venkataramani, S.K. Bose, K.R. Srivathsan, An exact model for the queuing analysis of MMPP/D/1 queue with non- preemptive priority for applications in ATM networks, Proc. ICCS-94, Singapore, 1994 pp. 104-108.
  • B. Venkataramani, S.K. Bose, K.R. Srivathsan, Queue length density and busy period distribution of MMPP/D/1 queue with non preemptive priority for use in ATM networks, Pro. ITC Seminar, Bangalore, India. 1993, 1993, pp.121-128

Published in National conference proceedings

  • S.Kumaravel, B.Venkataramani and Akila M, Behavioural Analysis of Clock Jitter Effects in Continuous Time Sigma Delta Modulator, VDAT July 7-9, 2011, Pune.

  • S.Kumaravel, B.Venkataramani, Ajit Randhir, and Ramakrishna Chowtri, A Novel Fully Differential Folded Cascode Operational Transconductance Amplifier, VDAT July 7-9 2011, Pune.

  • N. Sreekanth Babu, S. Ramasamy, B.Venkataramani, “Design of high performance current steering DAC using pattern search algorithm” , Proc. Of VLSI design and test symposium VDAT 2007, Aug 2007, Calcutta, India, pp. 120-129

  • S. Ramasamy, B.Venkataramani, N. Sreekanth Babu, “Design and implementation of 14 bit 200Msps current steering DAC using Gm/Id method”, Proc. Of VLSI design and test symposium VDAT 2007, Aug 200, Calcutta, India, pp.105 -113

  • V. Amudha, B.Venkataramani, J.Karthick and C. Praveen, “ SOC implementation of the neural network based isolated word recognition”, proceedings of VDAT 2006, pp. 130-138.

  • G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, “Design and FPGA implementation of wavepipelined image block encoders using 2D-DWT”, Proc. of VLSI design and test symposium VDAT 2005, Aug 2005, Bangalore, pp 12-20

  • G. Seetharaman, B. Venkataramani and G.Lakshminarayanan, Design and FPGA implementation of wavepipelined distributed arithmetic based filters, Proceedings of VLSI Design & Test workshop VDAT04, pp. 216-220, August 2004, Mysore

  • G. Lakshminarayanan, B. Venkataramani, M. Yousuff Shariff, T. Rajavelu and M. Ramesh, “Self tuning circuit for FPGA based wavepipelined multipliers”, Proceedings of VLSI Design & Test workshop VDAT04, pp. 93-101, August 2004, Mysore

  • J.Senthil Kumar , G.Sriram, G.Lakshminarayanan , B.Venkataramani, “ Design and Implementation of FPGA based Fast Multipliers with Optimum Placement & Routing Using Structure Organizer, National Conference on VLSI design & Testing, PSG College of Technology, Coimbatore, 21-22 February, 2003.

  • U. Uma Maheswari, H. Anand, S. Ramasamy,K Subramanyam, B.Venkataramani, G. Lakshminarayanan, “Performance evaluation of various schemes for FPGA implementation of 2D- DWT , National Conference on VLSI design & Testing, PSG College of Technology, Coimbatore, 21-22 February, 2003

  • B.Venkataramani, “High Performance DSP circuits using FPGAs”, Workshop on 'DSP/FPGA technologies' , CEERI Chennai, June 24-25 2002

  • M.C.Sundar, A.Senthil Kumar, B.Venkataramani, M. Bhaskar, “ Implementation Of FPGA Based Image Processing System With Lifting Wavelet Transform, Proc. Of National workshop on Computer Vision, Graphics and Image Processing, WVGIP 2002, TCE, Madurai, Feb 2002, pp 45-50

  • K.Balaji, B.Venkataramani, M.Bhaskar, G. Lakshminarayanan, Enhancing the Performance of the TI DSP systems with FPGAs, Texas Instruments DSPFEST-2001, Bangalore

  • B. Venkataramani, S.K. Bose, K.R. Srivathsan, Computation of Queuing delays of a non-preemptive MMPP/D/1 priority system, proc. National Communications Conf. 1997, I.I.T., Madras, India, 1997 pp. 12-16.

  • B. Venkataramani, S.K. Bose, K.R. Srivathsan, Queuing analysis of a non-preemptive MMPP/D/1/K priority system, Pro. National Communications Conf. 1996, I.I.T., Bombay, India,February 1996, pp. 243-246.